Sarance Technologies Releases 40GE and 100GE IP for General Availability
Ottawa – Sarance Technologies, the leading supplier of high speed interconnect Intellectual Property (IP) technology, announced today the immediate availability of HSEC (High Speed Ethernet Core), the world’s first commercially available Media Access Controller (MAC), Physical Coding Sublayer (PCS), and Multi Lane Distribution (MLD) IP conforming to the emerging 40Gigabit Ethernet (40GE) and 100Gigabit Ethernet (100GE) standard. Sarance Technologies has been an active member of the IEEE 802.3ba High Speed Ethernet (HSE) working group since its inception, and is one of the original contributors to the definition and implementation of the new architecture for 40G and 100G Ethernet protocols. The HSEC IP conforms to Draft 2.0 of the IEEE802.3ba standard and has been tested by major networking and service provider vendors in system laboratories and validated in field trials running over a trillion of error free Ethernet frames over a live 100GE network. The HSEC IP has also been proven to interoperate with a major test equipment vendor.
“With end user applications driving demand for bandwidth in the transport core and the data center, service providers understand the need for quick deployment of 40GbE and 100GbE.” said Jag Bolaria, senior analyst at The Linley Group. “Off-the-shelf IP Cores from vendors such as Sarance Technologies reduce development time and enable interoperability across multiple implementations, allowing service providers to build-out 40GbE and 100GbE in the core of their network.”
“The architecture of 100GE and 40GE systems is very different from traditional 10GE and 1GE systems as 802.3ba has introduced several new design concepts. The availability of HSEC IP from Sarance accelerates the development of 40GE and 100GE products and enables system developers to focus their resources on their value added and differentiating features.” said Farhad Shafai, founder and VP of R&D at Sarance Technologies.
The HSEC IP is available as soft core for Virtex®-5 TXT FPGAs and Altera Stratix® IV GT and Altera Stratix® IV GX FPGAs, as well as for ASIC implementations. It has also been implemented and validated in 65nm and 40nm process technologies. The IP is delivered as a netlist targeted for the specific FPGA architecture, or as RTL code that can be implemented in any ASIC process technology. In addition, Sarance will be demonstrating the HSEC IP running 100GE traffic at the OFC/NFOEC Convention in San Diego, California on March 24-26, 2009.
